1. Field of the Invention
The present invention relates to a solid-state imaging apparatus.
2. Description of the Related Art
In recent years, the numbers of pixels of solid-state imaging apparatuses are being increased to enhance the quality of captured images in image input apparatuses such as digital still cameras and digital video cameras. Image input apparatuses are also available which reduce costs by mounting an A/D converter in a solid-state imaging apparatus to realize a digital output.
One example of an A/D conversion system mounted in a solid-state imaging apparatus is a column A/D conversion system (for example, see Japanese Patent Application Laid-Open No. H05-48460).
A column A/D conversion system includes an A/D converter for each column of pixels, and operates the A/D converters in parallel. Hence, the column A/D conversion system can enhance the readout speed of a solid-state imaging apparatus. Meanwhile, accompanying the miniaturization of pixels, there are severe limitations with respect to the arrangement of the A/D converters provided for each column of pixels. Examples of the configuration of a column A/D converter include a configuration that has a counter and ramp signal generation circuit both in common with another A/D converter, and also includes in each column, a comparator that compares a sensor signal and a ramp signal, and a holding unit that holds data from the counter when the comparator performs a comparison and determines a result. When the number of A/D conversion bits is increased to obtain a high image quality, an operation clock of the counter increases in speed proportionally to 2 to the power of natural number n.
To lower the speed of the operation clock, a method is available that employs a two-step A/D converter that converts higher digit bits and lower digit bits into digital signals in a time-series manner. Examples of a two-step A/D converter include a device disclosed in Japanese Patent Application Laid-Open No. 2002-232291.
Further, to increase the readout speed of a sensor mounted in a column A/D converter, a method is available that outputs A/D conversion data of the previous row during A/D conversion of sensor output of a certain row. To implement this, a holding unit that holds the conversion data of the previous row is required.
According to the A/D conversion system disclosed in the aforementioned Japanese Patent Application Laid-Open No. H05-48460, there is the problem that because the circuit diagram illustrates a circuit in which respective holding units for each bit are arranged in parallel in the direction along a row, the interval between the pixels increases when elements are disposed as shown in the circuit diagram.
Furthermore, the sizes of pixels decrease with the increase in the numbers of pixels of solid-state imaging apparatuses. Due to such increase in the number of pixels, in solid-state imaging apparatuses including column A/D converters in which an A/D converter is provided for each column of pixels, it is increasingly necessary to efficiently arrange circuit portions other than the pixel array that includes the A/D converters. However, neither Japanese Patent Application Laid-Open No. H05-48460 nor Japanese Patent Application Laid-Open No. 2002-232291 teaches or suggests anything regarding the arrangement of holding units that hold data from a counter. If a case is assumed in which the wires between A/D converters and holding units that hold conversion data of the relevant previous row are arranged in parallel in the row direction as shown in the circuit diagram shown in FIG. 8 in Japanese Patent Application Laid-Open No. H05-48460, there is the problem that the width between the holding units of each pixel column increases.